As the performance of microprocessors improves, the power consumption tends to increase year by year, so that a problem surfaces where a semiconductor device such as a processor is difficult to be run with a maximum load that is allowed in the specification due to an upper limit of power supply performance and an upper limit of chip temperature. Hereinafter, a case in which, as a semiconductor device, a processor (CPU) is used as an example will be described.
The processor is requested to run so as not to exceed a power consumption upper limit and a temperature upper limit, and when the processor exceeds these limits, a malfunction may occur due to a signal delay and the like. Therefore, when the processor may exceed the power consumption upper limit and/or the temperature upper limit during normal operation, load is adjusted so as not to exceed the limits. As methods of adjusting the load, dynamic frequency scaling (DFS) and dynamic voltage and frequency scaling (DVFS) are known. The DFS is a method that changes the load by dynamically changing a clock frequency. The DVFS is a method that further reduces the power consumption by lowering an operating voltage by a voltage corresponding to a timing margin generated by lowering the clock frequency.
When performing the aforementioned methods, it is desirable that the processor is operated at high clock frequency as much as possible within a range not exceeding the upper limit of the load from a viewpoint of performance of the processor. As a method that causes the processor to operate at high clock frequency as much as possible within a range not exceeding the upper limit of the load, a method is generally performed in which a control threshold value is set below an upper limit value and when the load exceeds the threshold value, control to lower the clock frequency or a power supply voltage is started. Thereby, the clock frequency or the power supply voltage lowers, and the load reduces accordingly. When the temperature of the processor (LSI) is an operating restriction, a temperature threshold value for control is set, and when the temperature of the processor exceeds the temperature threshold value, the clock frequency is lowered. However, in a case in which the clock frequency is lowered when the temperature exceeds the temperature threshold value, there is a delay until the clock frequency actually lowers, so that the temperature rises continuously during that time.
In this control, if the temperature threshold value is lowered, the performance of the processor is generally lowered, so that it is desirable that the temperature threshold value is close to the upper limit temperature as much as possible. However, if the temperature threshold value is too close to the upper limit temperature, there may be a case in which the temperature exceeds the upper limit temperature in a period of time from when the temperature of the processor exceeds the temperature threshold value to when the clock frequency is lowered. Therefore, it is requested that the temperature threshold value is lowered by a value corresponding to a temperature rise during a delay time used for the frequency control.
A case in which the maximum temperature rise estimated in the above temperature control occurs is a case in which the power consumption changes to the maximum value in a stepwise manner by load variation. In this case, when the temperature exceeds the temperature threshold value, it is requested to lower the clock frequency to a clock frequency at which the temperature is lower than the upper limit temperature even when the maximum power is consumed.
If the power when the temperature exceeds the temperature threshold value is smaller than the maximum power consumption, the clock frequency does not have to be lowered in the manner as described above. However, when the frequency control is performed based on only detected temperatures, it is difficult to determine how much the temperature will rise eventually at the time point when the temperature exceeds the temperature threshold value, so that the frequency is lowered to the aforementioned frequency at all times so that the temperature does not exceed the upper limit even when the load variation is maximum. Therefore, such control causes degradation of performance.
As a countermeasure against the above, it is possible to indirectly estimate the temperature change by setting two temperature threshold values and measuring a temporal difference between times when the temperature exceeds the respective threshold values. However, in this case, a threshold temperature is lowered and a control delay increases in practice, so that the general performance of the processor degrades.
On the other hand, when the load decreases and temperature margin increases, to increase the frequency, a control is considered in which a threshold value for frequency control is set in the same manner as described above and the clock frequency is increased when the temperature falls below the threshold value. However, also in this case, it is difficult to determine how much the temperature will fall eventually by only temperatures at the time point when the temperature falls below the threshold value. Specifically, there may be a case in which the clock frequency is increased too much and the temperature exceeds the temperature upper limit. To avoid the above problem, the clock frequency is gradually increased. However, in such control, it takes time until an appropriate clock frequency is reached, so that the performance of the processor is uselessly degraded during that time.
To avoid such useless degradation of performance, a configuration is considered in which the power consumption is monitored instead of the temperature and the clock frequency is switched according to the value of power consumption. However, there are the following problems:
(1) A temperature restriction, which is an operating restriction, is converted into a power value by using a thermal resistance value which is the rating of the system and control is performed, so that a conversion error margin corresponding to a difference between the thermal resistance value and an actual thermal resistance is generated as compared with control directly using temperatures. The margin is considered, so that it is difficult to perform accurate control.
(2) In power control, an upper limit power corresponding to the upper limit temperature is set in advance. Therefore, even if the peripheral temperature changes and the temperature margin changes, the upper limit power does not follow the change of the temperature margin, so that it is not possible to follow the change of power margin accompanying the change of peripheral temperature.
As described above, the control based on the power consumption causes degradation of general performance due to various control margins. Further, it can be considered to perform control by using both temperature and power consumption observed by a temperature monitor and a power monitor. However, there is a problem that the control is complicated.
As described above, there is a semiconductor device such as a microprocessor, which has a sufficient power supply capacity but has a strict operation guarantee temperature condition and which has an operating condition in which an upper limit restriction of a junction temperature of the chip determines a maximum allowable load. In such a semiconductor device, it is desired to reduce the degradation of performance by controlling the clock frequency and further the power supply voltage if desired so that the chip temperature does not exceed the upper limit temperature.
The followings are reference documents:
[Document 1] Japanese Laid-open Patent Publication No. 2004-310785,
[Document 2] Japanese Laid-open Patent Publication No. 2012-221301 and
[Document 3] Japanese Laid-open Patent Publication No. 2003-140782.